AUTHORS: Alexandru Gabriel Gheorghe
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ABSTRACT: In the classical Op-Amp design some very simple expressions are used, based on a simplified circuit model. This could lead to a prototype whose response is not the desired one and the Op-Amp must be redesigned. Another possible case is when the designed Op-Amp's response is the desired one but only for a certain load, a different load could produce an undesirable behavior or an unstable response. In this paper a two stage Miller compensated Op-Amp, designed in 180nm CMOS technology is verified from the point of view of phase margin and is optimized from the settling time point of view. To this aim the phase margin symbolic expression of the Op-Amp in the open loop is computed starting from poles and zeros symbolic expressions. Using this expression, an analysis to evaluate the influence of the Miller and the load capacitance on phase margin is performed. This way, the designer can rapidly verify if the response of the Op-Amp is stable for various Miller and load capacitances. After that the symbolic expression of the time constant is estimated starting from the poles and zeros symbolic expressions of the Op-Amp in the closed loop, function of the Miller and load capacitances. The settling time is evaluated for various Miller and load capacitances values to find the optimum, smallest time response. The numerical results for phase margin and settling time obtained with this algorithm are compared with those computed with SPECTRE RF.
KEYWORDS: Op-Amp, pole/zero, phase margin, settling time, symbolic expressions, design verification, design optimization
REFERENCES:
[1] Z. Yan, P.I. Mak, R.P. Martins, 'Two Stage
Operational Amplifiers: Power and Area
Efficient Frequency Compensation for Driving
a Wide Range of Capacitive Load', IEEE
Circuits and Systems Magazine, (2011).
[2] H. J. Yang, and D. J. Allstot, “Considerations
for Fast Settling Operational Amplifiers,” IEEE
Trans. On Circ. and Syst., vol. 37, no. 3,
pp.326-34, (Mar. 1990).
[3] U. Chilakapati and T. Fiez, “Effect of Switch
Resistance on the SC Integrator Settling Time,”
IEEE Trans. On Circ. and Syst. II: Analog and
Digital Sig. Proc., vol. 46, no. 6, pp. 810-815,
(Jun. 1999).
[4] U. Chilakapati and T. Fiez, “Settling time
design considerations for SC integrators,” IEEE
Int. Symp. on Circ. And Syst., pp. 492-495,
(Jun. 1998).
[5] G. Palumbo and S. Pennisi, Feedback
Amplifiers Theory and Design. Boston, MA:
Kluwer, (2002).
[6] G. Palmisano, G. Palumbo and S. Pennisi,
“Design Procedure for Two-Stage CMOS
Transconductance Operational Amplifiers: A
Tutorial,” Analog Integrated Circuits and
Signal Processing, vol. 27, pp. 179-189, (2001).
[7] F. A. Amoroso, A. Pugliese, G. Cappuccino,
Design Considerations for Fast-Settling TwoStage Miller-Compensated Operational
Amplifiers, Electronics, Circuits, and Systems,
2009. ICECS 2009, (2009), Page(s): 5 – 8.
[8] A. G. Gheorghe, F. Constantinescu, “Pole/zero
computation for linear circuits”, 6-th European
Symposium on Computer Modeling and
Simulation, Malta, (Nov. 14-16, 2012).
[9] A. G. Gheorghe, F. Constantinescu, M.
Nitescu, 'Improved LR Algorithm for
Computation of the Approximate Symbolic
Pole/Zero Expressions', AFRICON 2013,
Mauritius, (9-12 sept., 2013).
[10] A. G. Gheorghe, F. Constantinescu, M. Niţescu
, 'State Matrix Simplification for Computation
of the Approximate Pole/Zero Expressions',
International Conference on Synthesis,
Modeling, Analysis and Simulation Methods
and Applications to Circuit Design (SMACD
2015), Istanbul, Turkey, (7-9 September 2015).
[11] A. G. Gheorghe, M. E. Marin, 'A Two Stage
Op-Amp Phase Margin Symbolic Expression',
22nd International Conference on Circuits,
Systems, Communications and Computers
(CSCC 2018), Majorca, Spain, July 14 - 17,
2018.
[12] I. W. Sanberg, H. C. So, “A two-sets-ofeigenvalues approach to the computer analysis
of linear systems”, IEEE Transactions on
Circuit Theory, vol. CT-16, No. 4 (November
1969), pp509-517.
[13] E. J. Davison, “On the calculation of zeros of a
linear constant system”, IEEE Transactions on
Circuit Theory, vol. CT-18, No. 1 (January
1971), pp. 183-184.
[14] Behzad Razavi, Design of Analog CMOS
Integrated Circuits, McGrawHill, (2001).
[15] A. G. Gheorghe, F. C., M. E. Marin, 'Symbolic
Formulas for Settling Time and Phase Margin
of Op-Amp with Arbitrary Number of Poles
and Zeros', XXVII International Scientific
Conference Electronics (ET 2018), 13 - 15
September 2018, Sozopol, Bulgaria. 1] Z. Yan, P.I. Mak, R.P. Martins, 'Two Stage
Operational Amplifiers: Power and Area
Efficient Frequency Compensation for Driving
a Wide Range of Capacitive Load', IEEE
Circuits and Systems Magazine, (2011).
[2] H. J. Yang, and D. J. Allstot, “Considerations
for Fast Settling Operational Amplifiers,” IEEE
Trans. On Circ. and Syst., vol. 37, no. 3,
pp.326-34, (Mar. 1990).
[3] U. Chilakapati and T. Fiez, “Effect of Switch
Resistance on the SC Integrator Settling Time,”
IEEE Trans. On Circ. and Syst. II: Analog and
Digital Sig. Proc., vol. 46, no. 6, pp. 810-815,
(Jun. 1999).
[4] U. Chilakapati and T. Fiez, “Settling time
design considerations for SC integrators,” IEEE
Int. Symp. on Circ. And Syst., pp. 492-495,
(Jun. 1998).
[5] G. Palumbo and S. Pennisi, Feedback
Amplifiers Theory and Design. Boston, MA:
Kluwer, (2002).
[6] G. Palmisano, G. Palumbo and S. Pennisi,
“Design Procedure for Two-Stage CMOS
Transconductance Operational Amplifiers: A
Tutorial,” Analog Integrated Circuits and
Signal Processing, vol. 27, pp. 179-189, (2001).
[7] F. A. Amoroso, A. Pugliese, G. Cappuccino,
Design Considerations for Fast-Settling TwoStage Miller-Compensated Operational
Amplifiers, Electronics, Circuits, and Systems,
2009. ICECS 2009, (2009), Page(s): 5 – 8.
[8] A. G. Gheorghe, F. Constantinescu, “Pole/zero
computation for linear circuits”, 6-th European
Symposium on Computer Modeling and
Simulation, Malta, (Nov. 14-16, 2012).
[9] A. G. Gheorghe, F. Constantinescu, M.
Nitescu, 'Improved LR Algorithm for
Computation of the Approximate Symbolic
Pole/Zero Expressions', AFRICON 2013,
Mauritius, (9-12 sept., 2013).
[10] A. G. Gheorghe, F. Constantinescu, M. Niţescu
, 'State Matrix Simplification for Computation
of the Approximate Pole/Zero Expressions',
International Conference on Synthesis,
Modeling, Analysis and Simulation Methods
and Applications to Circuit Design (SMACD
2015), Istanbul, Turkey, (7-9 September 2015).
[11] A. G. Gheorghe, M. E. Marin, 'A Two Stage
Op-Amp Phase Margin Symbolic Expression',
22nd International Conference on Circuits,
Systems, Communications and Computers
(CSCC 2018), Majorca, Spain, July 14 - 17,
2018.
[12] I. W. Sanberg, H. C. So, “A two-sets-ofeigenvalues approach to the computer analysis
of linear systems”, IEEE Transactions on
Circuit Theory, vol. CT-16, No. 4 (November
1969), pp509-517.
[13] E. J. Davison, “On the calculation of zeros of a
linear constant system”, IEEE Transactions on
Circuit Theory, vol. CT-18, No. 1 (January
1971), pp. 183-184.
[14] Behzad Razavi, Design of Analog CMOS
Integrated Circuits, McGrawHill, (2001).
[15] A. G. Gheorghe, F. C., M. E. Marin, 'Symbolic
Formulas for Settling Time and Phase Margin
of Op-Amp with Arbitrary Number of Poles
and Zeros', XXVII International Scientific
Conference Electronics (ET 2018), 13 - 15
September 2018, Sozopol, Bulgaria.
